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基于 cascode 结构的 Ka 频段 CMOS 功率放大器设计
甄建宇 1,陈娜 2
(1. 中国电子科技集团公司第十三研究所,河北 石家庄 050051;2. 中国电子进出口有限公司,北京 100036)

摘  要:文章通过分析共源共栅功率放大器的基本原理,提出了一种新颖的基于 cascode 级间电路结构,通过优化电路级 间的阻抗匹配的设计思路。同时采用 55 nm RF CMOS 硅基工艺设计并制作出一款工作于 Ka 频段的功率放大器。与传统的CMOS 功率放大器相比,具有高增益、低功耗、高功率等特点。经过实物加工及裸片测试,结果表明设计的功率放大器在工作频率为 27 ~ 32 GHz 时,小信号增益为 19 ~ 20 dB,输出 1 dB 压缩点为 12 dBm,最大饱和输出功率为 15 dBm,最大功率附加效率为 21.5%,该放大器芯片尺寸为 780 μm×710 μm。


关键词:功率放大器;共源共栅;CMOS



DOI:10.19850/j.cnki.2096-4706.2021.05.014


中图分类号:TN722                                     文献标识码:A                                    文章编号:2096-4706(2021)05-0060-04


Design of Ka Frequency Band CMOS Power Amplifier Based on cascode Structure

ZHEN Jianyu1 ,CHEN Na 2

(1.The 13th Research Institute of China Electronics Technology Group Corporation,Shijiazhuang 050051,China; 2.CEIEC,Beijing 100036,China)

Abstract:By analyzing the basic principle of cascode power amplifier,this paper proposes a novel design idea based on cascode interstage circuit structure,which optimizes the impedance matching between circuit stages. At the same time,a power amplifier working in Ka frequency band is designed and manufactured by using 55 nm RF CMOS silicon based process. Compared with the traditional CMOS power amplifier,it has the characteristics of high gain,low power consumption and high power. After physical processing and wafer testing,the results show that the power amplifier designed in this paper has a small signal gain of 19 ~ 20 dB,an output compression point of 1 dB of 12 dBm,a maximum saturated output power of 15 dBm,a maximum power additional efficiency of 21.5%,and a chip size of 780 μm×710 μm when the operating frequency is 27 ~ 32 GHz.

Keywords:power amplifier;cascode;CMOS


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作者简介:甄建宇(1987—),男,汉族,河北张家口人,工 程师,硕士研究生,研究方向:微波毫米波集成电路设计。