摘 要：：介绍了一款基于 GaAs 0.15 μm pHEMT 工艺的 2 ～ 18 GHz 超宽带低功耗低噪声放大器芯片的设计，给出了在片测试结果。该芯片采用结合有源偏置和并联负反馈技术的改进型共源共栅放大结构，该结构可以使放大器在超宽带的工作频带范围内实现低噪声、低功耗和较高增益，同时减小放大器性能对工艺波动的敏感程度。在 2 ～ 18 GHz 的超宽带频率范围内，该芯片实测噪声系数≤ 1.4 dB，增益≥ 14 dB，且具有 3 dB 的正斜率，输出 P-1 功率≥ 12 dBm，输入输出驻波≤ 1.6，整个芯片功耗仅为 0.15 W，芯片尺寸仅为：1.4 mm×1.1 mm×0.1 mm。
关键词：超宽带；低功耗；低噪声放大器芯片；有源偏置
DOI:10.19850/j.cnki.2096-4706.2023.01.013
中图分类号：TN72 文献标识码：A 文章编号：2096-4706（2023）01-0051-04
Ultra Wideband Low Power Consumption Low Noise Amplifier Chip
LIU Ying, WANG Cetian, WU Haifeng, LIAO Xuejie, WANG Wei
(Chengdu Ganide Technology Co., Ltd., Chengdu 610220, China)
Abstract: In this paper, the design of 2 ～ 18 GHz ultra wideband low noise amplifier chip based on GaAs 0.15 μm pHEMT process is introduced, and on wafer test results are presented. The chip uses and combines with the active bias and parallel negative feedback cascade amplifier structure, and the structure can make the amplifier achieve low noise, low power consumption and higher gain in the range of working frequency band of ultra wideband. At the same time, it reduces the sensitivity of amplifier performance to process fluctuations. In the 2 ～ 18 GHz ultra wideband frequency range, measured noise coefficient of the chip is less than and equal to 1.4 dB, a gain is more than and equal to 14 dB, and it has 3 dB Positive Slope, the output of P-1 power is more than 12 dBm, the input and output of VSWR are less than and equal to 1.6, and the power consumption of the chip is only 0.15 W. The chip size is only 1.4 mm×1.1 mm ×0.1mm.
Keywords: ultra wideband; low power consumption; low noise amplifier chip; active bias
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作者简介：刘莹（1986.05—），女，汉族，四川夹江人，高级工程师，硕士研究生，研究方向：射频微波毫米波芯片设计。